Most electrical systems are digital today and hence require analog-to-digital converters (ADCs) to interface to the outside world. The outside world can either be real world signals such as temperature, pressure, voice, etc., or modulated carriers transmitting information over some medium (analog or digital communication). For all applications, energy efficiency is extremely important and more so for battery operated systems.
Delta sigma modulators are widely used for high resolution, low speed ADCs as well as for medium resolution, high speed ADCs. Delta sigma modulators have high dynamic range which makes them robust for communication and signal processing areas. It is important to use a multi-bit delta sigma modulator to fulfill demand for higher resolution, wider bandwidth and low quantization noise power. A digital to analog converter (DAC) is used in a feedback path of the delta sigma modulator. The DAC includes multiple DAC elements. A major drawback of the multi-bit delta sigma modulator is non-linearity stemming from the mismatching between the DAC elements.
DAC glitches and finite rise and fall time results in erroneous integration of a pulse generated by DAC in a continuous time delta sigma modulator. This error in DAC is known as dynamic error of DAC. The dynamic error of DAC limits the performance of the delta sigma modulator by increasing noise and non-linearity. Methods are known to reduce the impact of DAC mismatch errors on performance of delta sigma modulators, but methods to reduce impact of dynamic error of DAC on the performance of delta sigma modulator are non-existent.